As compared with the wireless LAN system of the current IEEE802.11b/g, IEEE802.11a provides a data rate of about 5 times the current data rate, at least an overall system capacity of 20 times the current capacity as the standard for a novel wireless LAN based on the Orthogonal Frequency Division Multiplex (OFDM) for a demand for wide wireless communication. In a 5 GHz frequency band, a wireless LAN is shifted from 2.4 GHz to 5 GHz with the advantage of a high data rate. Incidentally, OFDM is an abbreviation of Orthogonal Frequency Division Multiplex. LAN is an abbreviation of Local Area Network.
Described in a non-patent document 1 (Teresa H. Meng et al, “Design and Implementation of an All-CMOS 802.11a Wireless LAN Chipsets”, IEEE Communication Magazine, August 2003, PP. 160-168) is that an IEEE802.11a wireless LAN system comprises a physical layer (PHY) and a media access layer (MAC), and the physical layer is based on the orthogonal frequency division multiplex (OFDM). A modulation technique using multi-carriers relaxes the effect of a multipath, and the OFDM distributes data into multi-carriers separated at accurate frequencies. This non-patent document 1 has described that the IEEE802.11a wireless LAN system comprises a CMOS RF transceiver chip and a digital baseband chip.
The RF transceiver comprises an RF receiver for reception, an RF transmitter for transmission and a frequency synthesizer. The frequency synthesizer generates an RF local signal and an IF local signal supplied to the RF receiver and the RF transmitter respectively.
Analog baseband transmission signals I/Q for the RF transmitter are generated by two D/A converters on the baseband chip. Analog baseband reception quadrature signals I/Q for the RF receiver are converted into digital signals by two A/D converters on the baseband chip prior to being processed by a baseband MAC processor.
Dual conversion has been adopted in architectures of the RF receiver and the RF transmitter without direct conversion being adopted therein. In the RF receiver, an RF reception signal is down-converted to reception baseband signals I/Q, based on the RF local signal and the IF local signal supplied from the frequency synthesizer.
In the RF transmitter, the analog baseband transmission signals I/Q are upconverted to an RF transmission signal, based on the RF local signal and the IF local signal supplied from the frequency synthesizer, followed by being amplified by a power amplifier.
In the digital baseband chip, the reception baseband signals I/Q from the receiver of the RF transceiver are supplied to the A/D converters. Digital signals corresponding to the outputs of the A/D converters are supplied to auto correlators via two FIR filters. The outputs of the A/D converters and the outputs of the auto correlators are supplied to a signal detection AGC unit, where the setting of reception gain of an analog front end is executed by the output of this unit. Signal detection, frequency offset evaluation and symbol timing all depend on auto correlation of a cycle or period training symbol supplied to a preamble.
The digital signals corresponding to the outputs of the A/D converters are supplied to one FIR filter, DC offset elimination unit, frequency rotator, fast Fourier transformer (FFT), channel selection filter and Viterbi decoder. Reception data for the media access layer (MAC) is generated from the output of the Viterbi decoder. The fast Fourier converter (FFT) shares an inverse fast Fourier transformer (IFFT) and hardware for the transmitter.
A transceiver corresponding to a 2.4 GHz wireless LAN has been described in a non-patent document 2 (Masoud Zargari et al, “Challenge in The Design of CMOS Transceivers for the IEEE 802.11 Wireless LANs; Past, Present and Future”, 2005 IEEE Radio Frequency Integrated Circuits Symposium, PP. 353-356). A SoC (system on chip) for single chip implementation, including a receiver for two-step downconversion, a transmitter for two-step upconversion, a frequency synthesizer and a baseband MAC unit has been adopted therein. The single chip implementation enables a wide bit-width interface between an RF transceiver and a digital baseband. The wide bit-width interface can be used in various analog/RF non-pairing calibrations.
An RF loop back is coupled between the output of a transmission RF mixer and the input of a reception RF mixer. A predetermined digital sequence is loop-back transferred to the corresponding receiver during calibration. The received digital codes are used for correction of RF non-pairing and RF carrier leaks like a DC offset and an I/Q mismatch.
A patent document 1 (U.S. Pat. No. 6,760,577, Specification of No. B2) has described that RF carriers used in a transmitter and a receiver of a direct conversion transceiver by a fractional phase-locked loop. A second pilot/tone fractional phased-locked loop is used to correct errors in I/Q phase and amplitude at the transmitter and receiver.
RF input terminals of two downconversion mixers of the receiver are supplied with an oscillation output signal of a pilot tone voltage-controlled oscillator of the second pilot/tone fractional phased-locked loop via a first coupler. Reception baseband signals I/Q corresponding to the outputs of the two downconversion mixers are supplied to a baseband digital signal processing circuit, and an error correction value is calculated by two programmable attenuators and two controllable phase shifters of the receiver.
A synthesized RF output of two upconversion mixers of the transmitter is supplied to one input terminal of a transmission I/Q mismatch monitor mixer of a second pilot/tone fractional phase-locked loop via a second coupler. The other input terminal of the transmission I/Q mismatch monitor mixer is supplied with an oscillation output signal of a pilot tone voltage-controlled oscillator of the second pilot/tone fractional phase-locked loop. A signal outputted from the transmission I/Q mismatch monitor mixer is supplied to the input of a logarithmic detector via its corresponding low-pass filter. An error correction value is calculated from the output of the logarithmic detector by two variable attenuators and two controllable phase shifters of the transmitter.
On the other hand, a patent document 2 (Japanese patent laid-open No. 2006-287900) has described a receiving circuit comprising a multi-stage programmable gain amplifier and a multi-stage low-pass filter supplied with I and Q reception baseband signals from quadrature reception mixers for downconversion of an RF analog LSI used in a cellular phone of the GSM type or the like. The characteristic of the receiving circuit suppresses a blocker level and reduces reception signal distortion. In the patent document 2, variations in the filter characteristics of the low-pass filters due to the manufacturing process of the RF analog LSI are corrected by a calibration circuit and control logic to prevent a bit error rate at reception from being deteriorated.
The calibration circuit includes an amplifier which supplies a reference clock signal to a low-pass filter at the first stage, and a digital phase shift circuit which delays the reference clock signal by the time corresponding to a delay time of the multi-stage programmable gain amplifier. The calibration circuit further includes a first limiter circuit coupled to the output of the phase shift circuit, a second limiter circuit coupled to the output of the final-stage low-pass filter and D-type flip-flops supplied with the outputs of both limiter circuits. The output of each D-type flip-flop is supplied to the control logic. The control logic determines which phase of the outputs of both limiter circuits is advanced, and generates a control code for changing over capacitance values of variable capacitors lying inside the low-pass filters.